HW / Design Engineers #901

•  B.Sc. in Electrical or Computer Engineering
•  At least 5 years experience as ASIC / VLSI Engineer, performing logic design (Verilog RTL Coding) or verification
•  Vast experience in complex design modules
•  Backend knowledge – advantage
design: J&J+A | dev: entry.
Copyright © 2011 DensBits. All rights reserved. | Memory Modem is a trademark of DensBits Technologies Ltd. | Terms Of Use | Privacy Policy